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Big Problems with ADCs generated code on KV31P100M120

Question asked by Mark Wyman on Oct 24, 2016
Latest reply on Jan 9, 2017 by Marek Neuzil

I have been fighting issues for a while on this processor and the dev platform TWR-KV31F120M attempting to use the two ADC cores on the above processor using the ADC_LDD bean. To me it appears this "bean" is incomplete at best. Whatever the case, it is producing inconsistent non-working code, especially if I change the setting for "Number of conversions" or "Result Type".

 

Problem 1: The Trigger portion of the GUI for ADC_LDD does nothing with the SIM_SOPT7 register, which is supposed to route the trigger signals from the selected timer/peripheral to the ADC core to trigger the conversions. This I found I had to manually add the SIM bean to my project, and manually edit the fields so the SIM_SOPT7 register was properly set up. Otherwise the ADC_LDD leaves this register at defaults and wont route any trigger signals to the ADC cores. Once the SIM bean is added to the project, it begins to interact with the Trigger settings of the ADC_LDD bean, and I had the loop triggering functioning... for a short while.

 

Problem 2: Even though I have the SOPT7 register properly setup, I only can occasionally get the ADC events for conversion complete to actually occur. At one point I had things working with Number of Conversions set to 1, and timing working, etc. While getting regular conversions, I ran into a problem where I was getting 8-bit signed values out left-shifted into position even though I had 16-bits signed selected. I went in and changed number of conversions to see if averaging had something to do with my problem. After this Number of Conversions change, I no longer get conversion complete events, the ADC bean claims things are always busy, even when I revert my settings.

 

It should not be timing, as I am only attempting to sample at a 1kHz rate to get things started before I turn up the speed.

 

Problem 3: I started playing with the settings trying to figure out the 8-bit problem, and realized the "Result Type" dropdown is not behaving correctly. I select "signed 16 bits, left justified", and click the down arrow again and I wind up with a different selection than what I asked for highlighted. It does not give me any confidence that what I selected is actually being generated. In fact it does appear to be quite incorrect and giving me 8-bit results instead of the 16-bits I am asking for.

 

 

So this combination of problems has me running around in circles simply trying to get regular sample timings on both ADC cores based on the PIT timer. The goal here early in this project is to use the two ADCs as a "scope" for debug purposes before utilizing them for a decision making process.

 

What is very frustrating is that I had it working, and now it doesn't even with reverted settings. 

 

What is the news with this processor and PE? Is there ongoing development and support, or am I getting killed by this NXP acquisition? Before this project, I never had any significant problems with PE.

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