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USART silicon errata? CTI w/o RDR

Question asked by Bo-Ming Tong on Oct 22, 2016
Latest reply on Nov 11, 2016 by isaacavila

It's a rare occurrence on a LPC11U35FHI33. IIR (the interrupt reason register) says UART interrupt is owing to CTI (character time-out), but LSR (line status register) is all zero. My ISR ends up in an infinite loop, because it reads the Rx FIFO only if the data ready bit is set, but there is nothing to read here as the Rx FIFO is empty. CTI won't clear without reading the Rx FIFO, so it keeps on reasserting the interrupt endlessly.

On the surface this seems something impossible to happen. If Rx FIFO is empty why can't CTI de-assert itself? Right now I (think I) have a workaround by reading Rx FIFO anyway even if it is empty, if it is a CTI and LSR says no data is ready.

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