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J-tag problems with SEGGER j-link Ultra+ and QWKS-SCMIMX6DQ

Question asked by Neil Turner on Oct 21, 2016
Latest reply on Oct 28, 2016 by Neil Turner



I am beginning a bare metal project using the QWKS-SCMIMX6DQ quick start board and am having problems using a SEGGER j-link Ultra+ j-tag module.


I am able to get connected to the board via the j-tag, but I cannot halt the CPU. This happens both using my development environment (Rowley Crossworks) and also if I used j-link Commander directly. I have posted the output from j-link commander below.


SEGGER recommended I use the device type of "MCIMX6Q4" which allows me to connect, but I still cannot halt the CPU. Is there anything else I need to configure either on the QWKS-SCMIMX6DQ board itself or in the software to make this work?





SEGGER J-Link Commander V6.10f (Compiled Oct 17 2016 17:41:50)
DLL version V6.10f, compiled Oct 17 2016 17:41:18


Connecting to J-Link via USB...O.K.
Firmware: J-Link Ultra V4 compiled Sep 1 2016 18:31:22
Hardware version: V4.00
S/N: 504401606
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref = 3.280V


Type "connect" to establish a target connection, '?' for help
J-Link>device MCIMX6Q4
Please specify target interface:
J) JTAG (Default)
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
Specify target interface speed [kHz]. <Default>: 4000 kHz
Device "MCIMX6Q4" selected.


TotalIRLen = 13, IRPrint = 0x0101


WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1
149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)




ARM AP[0]: 0x44770001, AHB-AP
ARM AP[1]: 0x24770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-003BB907 ETB
ROMTbl 0 [1]: 00002003, CID: B105900D, PID:04-002BB906 ECT / CTI
ROMTbl 0 [2]: 00003003, CID: B105900D, PID:04-004BB912 TPIU
ROMTbl 0 [3]: 00004003, CID: B105900D, PID:04-001BB908 CSTF
ROMTbl 0 [4]: 0000F003, CID: B105100D, PID:04-000BB4A9 ROM Table
ROMTbl 1 [0]: 00001003, CID: B105900D, PID:04-000BBC09 Cortex-A9
Found Cortex-A9 r2p10
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Data endian: little
Main ID register: 0x412FC09A
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
System control register:
Instruction endian: little
Level-1 instruction cache enabled
Level-1 data cache enabled
MMU enabled
Branch prediction enabled
Found 3 JTAG devices, Total IRLen = 13:
#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
#1 Id: 0x00000001
#2 Id: 0x2191C01D
Cortex-A9 identified.



WARNING: CPU could not be halted