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SSP0 Receive FIFO in LPC11U68J100

Question asked by jean valjean on Oct 18, 2016
Latest reply on Nov 3, 2016 by LPCX presso support



is it possible to see somehow in LPCXpresso the receive FIFO of LPC11U68J100 controller?

I'd like to check it, because I don't have the same data in SSP0_DR  what the master sends. The uC is configured as slave. I got the SSP0 interrupt, something comes in but not what I expect.

Signals are checked by oscilloscope, they're correct. I should have some SW issue there.


In case my uC is slave, should the internal SSP0 clock have exactly the same frequency, as the master has?


The chip is on OM13058 LPCXpresso board, I use LPCXpresso 8.1.4 on Win7.