We are using LPC4330FET180 in our design and still have die revC in stock. Please help us understand this OTP.2 issue discussed in "Errata sheet LPC4370, LPC4350, LPC4330, LPC4320, LPC4310" by sharing more detail about the following:
- What is the nature of the "repeated power cycling" that might cause this erroneous programming? How many power cycles and at what frequency of toggling the power causes the issue?
- Is the 2 ms delay in the suggested timing diagram intended to be minimum, nominal or maximum? What tolerances are permitted on the suggested 2 ms delay?
- Are there any issues if the delays are much longer than 2ms, say up to 20 - 30 ms?
- What is the voltage at which nRESET is deasserted? I've assumed VIH 0.8 x (Vps-0.35) based on datasheet. However, in our circuit, I see input current jump suggesting the IRC oscillator is starting when nRESET gets to about half rail.
- I think the example delay circuit will produce timings somewhat different than the conceptual waveform for the workaround. In particular the VDDIO and RESETN voltages will not remain at zero until after VDDREG, VDDA have reached their full value as drawn. Please advise if a delay scheme which clamps the VDDIO and RESETN at 0 V for the 2ms delay is essential.
Thank you for your help and comments.