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About iMX6 BT1120 progressive output issure

Question asked by xiong gao on Oct 17, 2016
Latest reply on Oct 19, 2016 by xiong gao


Hello everyone,I have a custom iMX6Q board running 3.0.35_4.1.0.

I need to send 1080P video through the parallel display port to FPGA,here is our hardware design

 

I am using the latest BT.1120 patch by Qiang Li to set the video mode to 1080P50(Patch to Support BT656 and BT1120 Output For i.MX6 BSP ( L3.0.35_4.1.0_GA_bt656_output_patch_2016-06-24))

 

my uboot parameter is "video=mxcfb0:dev=bt656,BT1120-1080P50,if=BT1120,fbpix=RGB24"

I also change the BT656_IF_DI_MSB from 23 to 15.

 

After apply those changes, we can get right pixel clock 148.5MHz,but we can't get right data at the FPGA side.

 

then we try to find if 576P works.After change uboot paramter to "video=mxcfb0:dev=bt656,BT1120-576P,if=BT1120,fbpix=RGB24",we can get right pixel clock 27MHz,and we can get right data at FPGA side,but the V Freq is 25 Hz(the correct Freq is 50 Hz)

I also tried to change the 576P refresh rate from 25 to 50 in the driver/video/mxc/mxc_bt656if.c , but it seems no effect.

 

Here is my question:

1.How can i make the BT1120-576P V freq to 50 Hz ?

2.What's wrong with 1080P or am i doing any thing wrong?

3.how to understand the iMX6 IPU DC microcode template ? is there any example or resource availabe?  

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