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Configuring EIM for ADV7391

Question asked by Ali Ismail on Oct 17, 2016
Latest reply on Oct 24, 2016 by Ali Ismail

I am currently working on integrating the ADV7391 with the i.MX6 SCM. I have followed along

and applied all the patches for the 3.14.52 kernel. I am currently running into the issue where I do not see a 27 MHz clock coming from the EIM to the ADV7391. I have configured my device device tree as follows.


imx6qdl-sabresd {
   pinctrl_ipu1_bt656: ipu1grp-3 {
      fsl,pins = <
         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x10
         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x10
         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x10
         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x10
         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x10
         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x10
         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x10
         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x10
         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x10

I have also created a patch to modify the IPU1_DI1_DISP_CLK to 27 MHz.

--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -792,7 +792,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
/* ipu clock initialization */
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); /* For CVBS 27MHz clock */
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);


I am not sure what else I am missing to ensure that the EIM provides the correct clock?