I use the 74HC4514 (4-to-16 line decoder/demultiplexer with input latches) in my design,
and put the logic diagram in LTSpice to simulate it.
To my surprise, it does the opposite as in the truth table on page 4 (see attached datasheet).
So A0-A3 = L L L L results in Q15 High, while A0-A3 = H H H H results in Q0 High.
On page 5 in the logic diagram, the latches have a bubble (circle) on the Sd and Rd inputs,
what does this bubble mean (why an OR port and bubble on the SR-inputs instead of a NOR port?)?
When using the OR ports (in front of latches) without inverted SR-inputs, the behaviour is as indicated in the truth table on page 4.
- datasheet (from NXP website)
- LTSpice simulation file (.asc)
- LTSpice simulation file (.png)
Thank in advance for your reply,
Original Attachment has been moved to: 74HC4514-(bubble-on-SR-inputs).asc.zip