We are facing issue with UART0 of K70 microcontroller during receive FIFO implementation.
Our Scenario:
We are using two K70 series micro controllers both having same functionalities in our design.
We have implemented UART Receive FIFO in both the micro controllers and 10 bytes of data packet is transmitted and received between these two controllers (Baud rate 115200, Packet transmit gap 10msec). Without any of our other peripherals being used the data communication works fine between the UARTs, the issue occurs only when our peripherals are enabled. The peripherals being used are UART, I2C, SPI, USB, Timers, etc. To narrow down the problem we disabled the SPI peripheral alone because we are transferring bulk data using this (SPI works at 5 Mhz, reads 16 bytes of data every 2 ms and using DMA for Data transfer) once it is disabled we do not face any issues.
Issue faced:
The communication (data transmission and reception) between the two controllers works for some time. After sometime we are unable to receive the data in one controller at that instant while debugging we find that the Framing error occurs (i.e FE bit is set in UARTx_S1 register). We have enabled the framing error interrupt and this error is cleared by reading the UARTx_S1 register and then reading the data register (D) inside ISR. However, at that instant we are not getting any interrupt being triggered therefore the Framing error (FE) is also not getting cleared and one micro controller stops receiving the Data in FIFO because FE intern stops the UART receive. This issue always happens in one controller.
Our question:
Can you please clarify us if there are any known issues with UART FIFO implementation related to framing error when bulk data transfer takes place via SPI DMA or any other peripheral?
Do you have any suggestion for us to overcome this situation?
