LPC541xx GPIO Port Direction Set Register.

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LPC541xx GPIO Port Direction Set Register.

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rogerlittlewood
Contributor I

On the GPIO port direction set/clear/toggle registers section 9.5.10 in the users manual. These only go up to bit 28 on port 0. Why not to bit 31?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Roger,

    After checking carefully with our according departments and the testing.

    This is really the document problem, register DIRSET[0:1], DIRCLR[0:1], DIRNOT[0:1] should go up to 31 bit, no reserved bit.  George already help to report this doc problem, the document will be updated in the next version.

    Sorry for the inconvenience we bring you.

Have a great day,
Kerry

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rogerlittlewood
Contributor I

There's another one I noticed. in the IOCON registers section 7.5.1 it says applies to pins P0 0-2 and P0 4-22, what about pin 3. And the same thing in Table 107 but here pins 2 & 3 are missing?

R

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ckphua
NXP Employee
NXP Employee

On 7.5.1 IOCON register (missing P0_3), I cannot find this issue on the UM10914 dated Sep 26, 2016. Please download the latest UM and post the exact register/page. Thanks

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Chee Kenong Phua,

     Thank you very much for your checking.

     Customer should mentioned UM10850.pdf which is the LPC5410X user manual, the latest user manual really have the problem which Roger mentioned.

    http://www.nxp.com/documents/user_manual/UM10850.pdf?fasp=1&WT_TYPE=Users%20Guides&WT_VENDOR=FREESCA... 

1. Page 91.

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2. Page 90

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Wish it helps you!


Have a great day,
Kerry

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ckphua
NXP Employee
NXP Employee

Thanks Kerry

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Roger,

      Thank you for your highlight.

      That should be also the document content missing problem.

      George already help to report all these doc bugs which you have mentioned, the problem will be fixed in the next doc reversion.

     Thanks  a lot!


Have a great day,
Kerry

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george_yan
NXP Employee
NXP Employee

Hi Roger,

It should be a docment typo. we have report it to our doc team.

Thanks,

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Roger,

    This should be related to the chip design, this register have this limitation.

    If you want to set the GPIO port direction, we suggest you to use the 9.5.3 GPIO port direction registers. This register support all the 32 bits.

Wish it helps you!

If you still have question, please let me know!


Have a great day,
Kerry

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ursaminor
Contributor II
If you want to set the GPIO port direction, we suggest you to use the 9.5.3 GPIO port direction registers. This register support all the 32 bits.

Doesn't make any sense to me...

I'm sure this will turn out to be a documentation error, and DIRSET0 has all relevant bits implemented. In particular bits 29...31 do exist and control GPIO0 port bits 29...31

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