AnsweredAssumed Answered

P2020 DDR3 signals pin delay

Question asked by Stefan Vranken on Oct 13, 2016
Latest reply on Oct 13, 2016 by Serguei Podiatchev


We are now doing pcb-layout of  P2020 using 4x DDR3 sdram with signals (ck, addr, cmd, control) in fly_by topology  just like on ddr3-udimm.  So we need our P2020 to do ddr3 write leveling to "length-match" our bytelanes with (ck, addr, cmd, control).

Signals (address, command, control) must be length-matched  ± 0.508 mm to ck per dram-chip.

To do this we also need to consider length of P2020-chip bond-wires to its bga balls. E.g. MA10 and MRAS are ~5mm apart on P2020 package.

Is there a (excel) list of bondwire lengths of P2020 ddr3 signals ? Does there exist an orcad symbol of P2020 with DDR3-pin-delays included ?

Kind regards,