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About OE assertion period of EIM in i.MX6DQ.

Question asked by Keita Nagashima on Oct 13, 2016
Latest reply on Oct 14, 2016 by Keita Nagashima

Dear All,

 

Hello. 

Refer to description of "OEA" bit in EIM_CSnRCR1 register on IMX6DQRM (Rev.3).

"In muxed mode OE assertion occurs (OEA + RADVN + RADVA + ADH +1) EIM clock cycles from start of access."

 

But, my customer measured the OEA signal on their custom board.

The result was (OEA + RADVN + RADVA + ADH + BCD + BCS +1).

 

On the other hand, refer to description of "RADVN" bit.

"ADV negation occurs according to the following formula:
(RADVN + RADVA + BCD + BCS + 1) EIM clock cycles from start of access."

 

[Question]

Is the following formula right?

"OE assertion = OEA + RADVN + RADVA + ADH + BCD + BCS +1"

 

i.e) is the description of Reference Manual typo?

 

Best Regards,

Keita

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