We are currently writing a driver to run a TDM transparent link with the QuiccEngine on a T1040 processor.
For this purpose we use UCC1 in fast mode, connected to TDM A.
As explained in QEIWRM chapter 22.8 we have made the following configurations :
1 - configured the SI RAM entries
2 - configured the SI registers
3 - connected UCC1 to the SI
4 - connected the CLK8 to SI Rx side and CLK 9 to Tx side
5 - configured UCC registers and parameters RAM
6 - Enabled the TDM through SIGLMRH register
7 - Initialized UCC 1 in Tx and Rx by writing 0x02010000 to CECR register
8 - Enabled UCC1 through GUMR register
We observe that the link doesn't work : the "ready" TxBD are not processed by the QuiccEngine, neither the RxBD are filled.
Nevertheless, it seems the clock anf frame sync are correctly seen since the SI SITARC and SIRARC registers are incremented.
It seems that there is an SDMA bus error generated just after step 7. According to SDSR, SDTA1 and SDTM1, this error is related to UCC1 Rx and the faulty address is the RxBD one.
When trying to perform step 7 with only Tx initialization (no Rx initilalization), the same error is produced (but a bit later), with UCC1 Tx and TxBD address.
Once such an error is generated, it seems that the UCC 1 is disabled.
The SDMA SDMR register is set to 0x02882888 value and its buffer base to MURAM + 0x1000.
Does someone have an idea about why the SDMA fails to access the TxBD / RxBD?
Thank you for your support,