Hi, I interfaced DS1307 I2C RTC with 9s12XDP512. I am able to write and read time information. But to read time continuously i had to write again the register address after first read operation. i generated stop condition in first read and again start in second read. Now it is showing as bus busy(IBB) in the second read operation which it should not occur after MS_SL=0 (stop condition) in first time read.
Can anybody tell how to resolve it??
Hi Taj,
Maybe you should check with Maxim how exactly does the DS1307 RTC operates.
DS1307 64 x 8, Serial, I²C Real-Time Clock - Maxim
I think this is normal. After each read or write, in case there isn't auto-incrementing address register, you should generate stop condition and then start all over again:
- generate start condition,
- call RTC (slave address),
- send register address,
- read or write register,
- generate stop condition.
If you put this in a loop, there you can have continuous reading of the time register. Here is a code snippet that can be of help:
//=============================================
for(;;) {
IIC0IBCR_MS_SL = 1; //Generate START condition
//------------------------------ CALL RTC DEVICE -----------------------------
IIC0IBDR = 0xA2; //Load slave address into IIC data register
while(!IIC0IBSR_IBB){} //Wait for flag to set indicating the bus is busy
while(!IIC0IBSR_IBIF){} //Wait for data transfer complete (TCF bit set)
IIC0IBSR_IBIF=1; //This bit must be cleared by SW, write a one to it
while(IIC0IBSR_RXAK){} //Wait for acknowledge from slave
//---------------------------- SEND DATA BYTE TO RTC -------------------------------
IIC0IBDR = RegAddr;
while(!IIC0IBSR_IBIF){} //Wait for data transfer complete (TCF bit set)
IIC0IBSR_IBIF=1; //This bit must be cleared by SW, write a one to it
while(IIC0IBSR_RXAK){} //Wait for acknowledge from slave
//---------------------------- R/W DATA BYTE FROM/TO RTC -------------------------------
IIC0IBDR = ReadRegData;
while(!IIC0IBSR_IBIF){} //Wait for data transfer complete (TCF bit set)
IIC0IBSR_IBIF=1; //This bit must be cleared by SW, write a one to it
while(IIC0IBSR_RXAK){} //Wait for acknowledge from slave
IIC0IBCR_MS_SL = 0; //Generate STOP condition
small_delay(); //may not be necessary
}
//=============================================
Hope the information helps.
Have a great day,
iggi
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