Does the iMX6 support two single channel dual rank LPDDR2?

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Does the iMX6 support two single channel dual rank LPDDR2?

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eduardoferrufin
Contributor II

Hello iMX community.

I have a question about connecting dual die LPDDR2(MT42L256M32D2LG-18 WT:A Single Channel Dual Rank) to the iMX6 (MCIMX6Q6AVT10AD). It appears that I do not have sufficient CLK_EN and CS lines to make this configuration work. Is there a way to configure extra clock enable and chip select lines on the iMX6?

Each chip contains dual 4Gb die, so in total if I can make this work, I will end up with 2GB.

Much appreciated

-Eddie

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eduardoferrufin
Contributor II

Igor

Table 44-7 Lists four Chip select lines being available in LPDDR2 mode. I have no reason to believe that I cannot use LPDDR2(MT42L256M32D2LG-18 WT:A Single Channel Dual Rank).

Do you agree?

Eddie

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igorpadykov
NXP Employee
NXP Employee

right, for lpddr2 mappimg is different so Table 44-7 should be used:

four chip select lines

Best regards
igor

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eduardoferrufin
Contributor II

Igor,

I found the below excerpt in the iMX6 Reference Manual

44.4.4.1 Address decoding
MMDC supports up to two consecutive chip selects, each with the same density. In
LPDDR2-2ch mode, up to two chip selects per channel are supported.
It is optional to configure the partition between the chip selects through
MDASP[CS0_END].
The incoming AXI address bus is 32 bits. MMDC decodes each access as follows:

Is it possible to have 4 chip selects coming from the MMDC controller?

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igorpadykov
NXP Employee
NXP Employee

Eddie

DRAM_CS[1:0]  - from Table 44-2. MMDC External Signals i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

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igorpadykov
NXP Employee
NXP Employee

Hi Eddie

I believe you are right, these two chips can not be used with i.MX6Q,

below presentation which provide more details about MMDC

DRAM Controller Optimization for i.MX Application Processors 

Best regards
igor
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