When setting the PLL configuration of the RCW of our custom LS1020a board for a 800 MHz core clock in the way as recommended in the LS102xa reference manual booting Linux fails. The reason is that QorIQ frequency driver changes the core clock to 1600 MHz.
When using the following configuration RCW PLL configuration Linux boots successfully:
CGA_PLL1_RAT = 00_1000 = 8 (our reference clock frequency is 100 MHz)
C1_PLL_SEL = 0000 = CGA_PLL1 /1
However the reference manual states:
For less than 1 GHz operation:
The value of this field should be twice the required core clock frequency and C1_PLL_SEL should be set to 4’b0001 (CGA_PLL1/2). For example, to achieve 800 MHz core clock frequency with reference clock frequency of 100 MHz, the ratio should be 16 (0x10) for locking the CGA PLL1 at 1600 MHz and C1_PLL_SEL=4’b0001 to achieve 800 MHz core clock frequency
With this PLL RCW configuration booting Linux fails.
My questions are:
- What are the disadvantages of using the non recommended PLL RCW settings?
- How can the Linux kernel be configured such that it does not select 1600MHz core frequency by overriding the CGA_PLL1/2 setting of the RCW by CGA_PLL1/1?