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Change System/Core Frequency - KL43

Question asked by Santhosh Ramani on Oct 5, 2016
Latest reply on Oct 7, 2016 by isaacavila

Hello,

 

I'm trying to update the system frequency for the hello world program running on the FRDM board. I updated the core frequency value to 24 MHz and changed the CLKDIV1 value to divide IRC48M by 2. I also configured the SysTick to provide an interrupt once every 0.5 seconds and use the Red and Green LED toggle to verify the frequency for SysTick.

 

However, the UART debug console is now working with a wrong baud rate. (The prints are gibberish and the echo feature is also gibberish). I have gone through the Debug code and can't find any reference to system clock other than specific function calls that read the value (ie there is no hard coded value that I could find).

 

Can someone please let me know what I'm missing? Here is the code that I modified in clock_config.c

 

/* Configuration for enter RUN mode. Core clock = 24000000Hz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgliteConfig =
{
.outSrc = kMCGLITE_ClkSrcHirc,
.irclkEnableMode = 0U,
.ircs = kMCGLITE_Lirc8M,
.fcrdiv = kMCGLITE_LircDivBy1,
.lircDiv2 = kMCGLITE_LircDivBy1,
.hircEnableInNotHircMode = true,
},
.simConfig =
{
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0U,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
.coreClock = 24000000U, /* Core clock frequency */
};

 

Thank you for your help. michaelsteffenfae Camron Chilton

Regards

 

Santhosh

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