AnsweredAssumed Answered

Flexbus MRAM 4M size write duplication

Question asked by Evgeni Kosakovski on Oct 3, 2016
Latest reply on Oct 27, 2016 by isaacavila

Hi.

 

I am working with K61 MCU and MR2A16ACYS35 SRAM (4M size) through Flex Bus. I can write to and read from MRAM.

The problem: when I write to address 0x60000000 any data, the same data I view at addresses 0x60080000, 0x60100000. The same situation occurred when I write to one from these addresses (0x60080000 or 0x60100000) - the data updated in every 512K part at addresses: 0x60000000, 0x60080000, 0x60100000.

Why occurred write duplication? How can I correct this?

 

Thanks. 

 

My configuration is:

 

// HW initialisation

#define MRAM_START_ADDRESS(*(volatile unsigned char*)(0x60000000))


FB_CSAR0 = (unsigned int)&MRAM_START_ADDRESS; //Set Base address

FB_CSCR0 = FB_CSCR_PS(1)       // 8-bit port
         | FB_CSCR_AA_MASK     // auto-acknowledge
         | FB_CSCR_WS(0x2)     // 2 wait states

FB_CSMR0 = FB_CSMR_BAM(0x3F)    // Set base address mask for 4M address space - up to 0x60400000
         | FB_CSMR_V_MASK;     // Enable cs valid signal

// Enable the clock to the FlexBus

SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; 

// FlexBus Clock not divided  
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x0);

// Set the GPIO ports clocks
SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
PORTB_PCR11 = PORT_PCR_MUX(5); // fb_ad[18]
PORTB_PCR16 = PORT_PCR_MUX(5); // fb_ad[17]
PORTB_PCR17 = PORT_PCR_MUX(5); // fb_ad[16]
PORTB_PCR18 = PORT_PCR_MUX(5); // fb_ad[15]
PORTC_PCR0  = PORT_PCR_MUX(5); // fb_ad[14]

PORTC_PCR1  = PORT_PCR_MUX(5); // fb_ad[13]
PORTC_PCR2  = PORT_PCR_MUX(5); // fb_ad[12]
PORTC_PCR4  = PORT_PCR_MUX(5); // fb_ad[11]
PORTC_PCR5  = PORT_PCR_MUX(5); // fb_ad[10]
PORTC_PCR6  = PORT_PCR_MUX(5); // fb_ad[9]
PORTC_PCR7  = PORT_PCR_MUX(5); // fb_ad[8]
PORTC_PCR8  = PORT_PCR_MUX(5); // fb_ad[7]
PORTC_PCR9  = PORT_PCR_MUX(5); // fb_ad[6]
PORTC_PCR10 = PORT_PCR_MUX(5); // fb_ad[5]
PORTD_PCR2  = PORT_PCR_MUX(5); // fb_ad[4]
PORTD_PCR3  = PORT_PCR_MUX(5); // fb_ad[3]
PORTD_PCR4  = PORT_PCR_MUX(5); // fb_ad[2]
PORTD_PCR5  = PORT_PCR_MUX(5); // fb_ad[1]
PORTD_PCR6  = PORT_PCR_MUX(5); // fb_ad[0]
PORTB_PCR20 = PORT_PCR_MUX(5); // fb_ad[31] used as d[7]
PORTB_PCR21 = PORT_PCR_MUX(5); // fb_ad[30] used as d[6]
PORTB_PCR22 = PORT_PCR_MUX(5); // fb_ad[29] used as d[5]
PORTB_PCR23 = PORT_PCR_MUX(5); // fb_ad[28] used as d[4]
PORTC_PCR12 = PORT_PCR_MUX(5); // fb_ad[27] used as d[3]
PORTC_PCR13 = PORT_PCR_MUX(5); // fb_ad[26] used as d[2]
PORTC_PCR14 = PORT_PCR_MUX(5); // fb_ad[25] used as d[1]
PORTC_PCR15 = PORT_PCR_MUX(5); // fb_ad[24] used as d[0]
PORTB_PCR19 = PORT_PCR_MUX(5); // fb_oe_b
PORTC_PCR11 = PORT_PCR_MUX(5); // fb_rw_b
PORTD_PCR1  = PORT_PCR_MUX(5); // fb_cs0_b
PORTD_PCR0  = PORT_PCR_MUX(5); // fb_ale

  

For read and write test:

uint8 wdata8 = 0x5A;           // data to write to mram
uint8 rdata8;                  // variable to read mram
for(n=0x00000;n<0x000F;n++)    // address offset
{
    *(vuint8*)(&MRAM_START_ADDRESS + n) = wdata8;
    rdata8 = 0x00;             // clear data variable
    rdata8 = (*(vuint8*)(&MRAM_START_ADDRESS + n));
}

 

Attachments

Outcomes