question about DRAM_SDCKE length and the exact position of ATDTW and RL

[利伟庄]

I have three question.

1.In the document of IMX6DQRM Rev. 3, 07/2015 in page 5487 the bit ATDTW is bit12 but in uboot code or IMX6DQRM revC the bit is bit14 .Is it be changed or the old document is error. if it is be changed which vesion of the chip begin apply this change.

2.All the document even in uboot code the in usb host queue head word1 the RL is bit 28-31 the C is bit 27 but in IMX6_SDK\sdk\drivers\usb\usbdefines.h the RL is bit 27-31 the C is bit 28 .Is the usbdefines.h error?

3.In Hardware Development Guide page 41
DRAM_CS[1:0]
DRAM_SDCKE[1:0]
DRAM_SDODT[1:0]
is to be Control signals group. the min length should be clock length -200 mil the max length should be clock length but in MCIMX6Q-SMART DEVICE BOARD Design LAY-27392_C.brd
DRAM_SDODT0 1783.35 mil
DRAM_SDCKE0 1384.84 mil
DRAM_CS0_B 1716.15 mil
CLOCK 1851.05 mil
the DRAM_CS and DRAM_SDODT is comply with the Hardware Development Guide but DRAM_SDCKE does not comply with the Hardware Development Guide it is about clock length -400 mil. if I lay new board should I comply with the Hardware Development Guide to make the DRAM_SDCKE length in clock length -200 mil ---clock length or should I make the DRAM_SDCKE length to be about clock length -400 mil like the DemoBoard? which is the best?

[Yuri · Accepted solution]

Hello,

  Please look at my comments below.

1.

The i.MX6 RM, rev.3 is correct regarding bit ATDTW, which is bit12

2.

The i.MX6 RM is correct regarding bits RL (28-31) and C (27) of

usb host queue head word1. This meets EHCI.

3.

  Please follow the Hardware Development Guide.

Have a great day,
Yuri

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[TomE]

> The i.MX6 RM, rev.3 is correct regarding bit ATDTW, which is bit12

Are you sure?

I think I've spotted a problem with the documentation of this bit. The "Assumed Answered" tag on this post means that if I ask a follow-up question in this thread it is unlikely to be addressed. So I'll create a new post and reference this one.

Tom