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Question asked by maticmohorcic on Sep 30, 2016
Latest reply on Oct 7, 2016 by Serguei Podiatchev



I'm designing power supply for T1040 and I have got question regarding it's sequence – step 2 (VDDC, VDD, USB_SVDD, S1VDD).  We will not use Deep Sleep functionallity.  In DS there is written that  When Deep Sleep is not used, it is recommended to source VDD and VDDC from same power supply. But in AN4825 there written that VDDC should ramp before VDD.

I'm studying T1040 reference design but there is something unclear for me. On the page 29 there is VCORE and VCORE_SLP and both outputs are connected together. But there are 2 mosfets on the page 31 which separates VCORE_SLP and VCORE => It is quite confusing


Do we need to use FET to separate VDDC and VDD ( different power up timing) or not?


Could you please answer my question asap because we are finishing our project.


Best Regards Matic