I've found a possible error in the LPC81x User Manual. I would like to determine if this really is an error, and if this is a good place to contact NXP about it, or whether I should choose some other channel.
This is about the LPC81x User Manual (UM10601), Rev. 1.6, from 2 April 2014 (direct link: http://www.nxp.com/documents/user_manual/UM10601.pdf). As far as I can tell, this is the latest version.
Table 3 (page 12, section 3.3.1) contains a list of interrupt sources. The interrupts in this table correspond to the bits in various NVIC registers, namely ISER0, ICER0, ISPR0, ICPR0, and IABR0. As far as I can tell, the bits in those registers are completely identical (i.e. the same interrupts are assigned the same bits).
Here's the problem: Table 3 indicates that interrupt number 14 is reserved. The documentation of the mentioned registers (for example, ISER0, table 5, page 16, section 3.4.1) has an interrupt at bit 14. In the case of ISER0, ISE_FLASH. I couldn't fint any references to a flash-related interrupt in the user manual, so I'm guessing table 3 is correct and the register descriptions are in error.
I have two questions now:
- Does interrupt 14 indeed not exist (i.e. is table 3 correct)?
- Is anyone from NXP reading this? Ideally, the mistake would get fixed in the user manual.