I'm asking a question about the MC33908 SBC in companion to a MPC5744P. We've noticed some strange behaviour on the FS0 output during a requested reset of the processor.
The attached trace shows !RST in yellow and !FS0 in green. The falling edge of !RST is caused by a request from the microprocessor over SPI to the SBC to have its reset line asserted. This will cause the fail-safe state machine go back to its init state, and cause FS0 to become asserted.
As you can see, !RST is released after 16ms - but look at the voltage level of FS0 - it certainly isn't a convincing digital
After !RST is de-asserted, software starts again going through the complete initialisation of the SBC again, including the fail-safe state machine, watchdog, and zeroing of the reset error counter.
After all that is done, software attempts to have FS0 de-asserted. I assume this happens more or less at the time where there is a step in the green trace - 10ms after software start would be about right.
As you can see, FS0 is not at a valid voltage level thereafter - not surprisingly, connected fail-safe outputs are inhibited.
The circuit on the FS0 pin is pretty much as recommended; a 10nF capacitor to ground, 5k6 pull-up to 3V3, 5k6 in series to the rest of the world - which in this case is all CMOS logic devices (3 off).
Interrogation over SPI of the WD_ANSWER register shows that it thinks FS0 is de-asserted and everything is perfectly fine.
Has anyone else seen the FS0 do that?
Thanks in advance for any suggestions.