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MPC5554 Unable to flash invalidate cache

Question asked by OLIVIER SCHLOSSER on Sep 23, 2016
Latest reply on Feb 6, 2018 by OLIVIER SCHLOSSER

Hi,

 

I have a problem with MPC5566.

 

When I'm trying to invalidate the L1 cache memory using CFI bit in L1CSR0 register, it sometimes fails (Rise of CABT bit).

The cache is configured in "write-through" mode and the invalidation is done at start of each decrementer exception.

 

My software implements the errata e1031 (http://www.nxp.com/files/32bit/doc/errata/MPC5554_REVB.pdf?fasp=1&WT_TYPE=Errata&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf)

 

Can someone confirm that cache invalidation is impossible in this specific case ? Have you a workaround ?

 

Please find below my source code:

;**************************************************************
; Global function : CacheInvalidate                           *
;**************************************************************
        .global CacheInvalidate
CacheInvalidate:
    mflr    r12                           ; save off return address in NV reg

    ; ERRATA e1031
    ; Disable external interrupts MSR[EE] = 0
    ; Disable critical interrupts MSR[CE] = 0
    ; Save the interrupt controllers current priority INTC_CPR[PRI]
    ; Raise the interrupt controllers current priority to maximum INTC_CPR[PRI] = 0xF
    ; Synchronize by executing msync and isync instructions
    ; Execute Invalidation of Cache
    ; After cache invalidation perform the following steps:
    ; Restore the saved priority setting to INTC_CPR[PRI]
    ; Restore MSR[CE] if it was altered
    ; Restore MSR[EE]
   
    mfmsr  r11
    lis    r3, 0xFFFD        # CE = 0
    addi   r3, r3, 0x7FFF    # EE = 0
    and    r3, r3, r11
    mtmsr  r3                # Disable MSR[EE] and MSR[CE]
   
    ; Base address of INTC_CPR = 0xFFF48008
    lis     r13, 0xFFF4
    ori     r13, r13, 0x8008
    lwz     r5, 0x0(r13)        # r5 contains the INTC_CPR[PRI] content
    li      r6, 0x000F
    stw     r6, 0x0(r13)       # set INTC_CPR[PRI] to 0xF
   
    InvalidateCache_l:
    ; Before writing to L1CSR0, execute msync & isync
    ; Invalidate cache: Set L1CSR0[CINV] to 1, other fields unchanged
    mfspr  r3, l1csr0
    ori    r3, r3, 0x0002
    msync
    isync
    mtspr  l1csr0, r3
   
    WaitForInvalidationComplete_l:
    ; Get current status of cache from spr L1CSR0
    ; Mask out all bits except CINV
    ; Compare if CINV, bit 30 is set to 1
    mfspr  r3, l1csr0
    and    r3, r3, r4
    cmpli  r3, 0x0002
    beq    WaitForInvalidationComplete_l
   
    ; Branch to error if cache invalidation was aborted
    ; Get current status of cache from spr L1CSR0
    ; In a scratch register set bit 29 L1CSR0[CABT] to 1, other bits 0
    ; Mask out all bits except CABT
    ; Compare if CABT, bit 29 is set to 1
    ; If there was an aborted invalidation, attempt again
    mfspr  r3, l1csr0
    li     r4, 0x0004
    and    r3, r3, r4
    cmpli  r3, 0x0004
    beq    InvalidateCache_l
   
    ; ERRATA e1031 continue
    ; Restore the saved priority setting to INTC_CPR[PRI]
    ; Restore MSR[CE] if it was altered
    ; Restore MSR[EE]
    stw     r5, 0x0(r13)
    msync
    isync
    mtmsr   r11

    mtlr    r12                           ; get saved return address
    blr

 

Thanks.

 

Best regards,

Olivier

 

 

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