I have a question regarding the DPAA related documentation, namely the "QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual".
In Section 6.2.1 the first phrase is "In the P1023, P2041, P3041, P4080 and P5020: The software portals of the QMan are mapped in a 2 MB area of system memory space, aligned on a 2 MB boundary."
This makes me think that the size of all software portals is 2MB and it cannot be greater. Am I right?
If yes, this seems to be in contradiction with the next one which is "The software portals are accessible as a target, via the local access windows (LAWs) used to define the system memory map. In the P2041, P3041, P4080 and P5020: One of the LAWs must be programmed by software with the target ID, base address, and size of the window in system memory occupied by the QMan’s software portals."
According to this, it seems that one can choose different sizes (not necessarily 2MB) so long they are compatible with the format of the SIZE filed in the chosen LAW Attribute register (see T4240RM Section 2.4.3).
However, later in the document, one can find that a 4080-like processor has 10 software portals where each is 16KB.
I would appreciate if a NXP employee will check this.