Hi, I'm a bit confused at the MCG block diagram for the KL82Z and I think there's a mistake.
Looking at KL82P121M72SF0RM, Figure 29-1, the PLL subsection of the MCG block diagram doesn't match the calculation of MCGPLL0CLK and MCGPLL0CLK2X described in step 3b of 184.108.40.206 Example 1. Specifically, the way the diagram is drawn makes it look like the PLL will inherently multiply by 2 before the effects of VDIV because VCOOUT is taken from AFTER the /2 block. I think it should looks something like the following:
I used a similar diagrams in this article for reference: