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8641D, execution units visibility during debug?

Question asked by William Martin on Sep 21, 2016

We are having a few machine check exceptions we're trying to understand.  The first, we've narrowed down to handling data outside of our array boundary by 1, but we don't see how the assembly code could translate into such a thing.   So, we're left questioning Instruction re-ordering into the pipeline.  Do we have any visibility into the pipeline?  What methods can we do to rule out the instructions have been re-ordered? 



Failure is MSSR->TEA bit set to 1, on a read operation, with the MPXCM->EADR register pointing to a 0xBxxx_xxxx address.  This address space shouldn't be used by anything in our source.