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I2C-bus timing

Question asked by Mikael Stolt on Sep 20, 2016
Latest reply on Sep 29, 2016 by Mikael Stolt


we are using the I2C1 interface of  LPC1769 in an equipment where we have to communicate through some opto-couplers. Since the equipment is designed for hazardous/explosive areas we cannot handle the opto-couplers the way we want, so the link is very slow with big delays from master to slave, and back again.

This complicates things a bit, especially when trying to get the equipment  through EMC test. The signal delays tends to make false start and stop conditions which messes up things.

The question thes is, does anyone know a good way to Control the timing between SCL and SDA pins?

All I can find is how to alter the duty-cykle of the SCL which might be useful.


I cannot find any help from any CPU register so I am stuck with using capacitors on the data-line to improve immunity.

Anyone with a better solution?