AnsweredAssumed Answered

TLB mappings above 4G in tcl

Question asked by Christian Reedy on Sep 20, 2016
Latest reply on Sep 27, 2016 by Yiping Wang

I am trying to setup a baseboard project that runs out of SRAM that initializes the DDR controllers and then performs tests on the memory. I am using a T4240QDS to test. The following memory map is desired:

# 0x00000000 0x001FFFFF TLB1_1 SRAM 2M
# 0xFE000000 0xFEFFFFFF TLB1_2 CCSR 16M

# 0x200000000 0x3FFFFFFFF TLB_7 DDR 8G

 

The DDR initialization appears to be working correctly as I can read and write the memory via the code warrior memory view. When I add the following TLB entry so the processor can access the DDR memory the program gets a program exception.

 

# define 8GB TLB entry 7 : 0x200000000 - 0x3FFFFFFFF for SRAM1 cache-inhibited
reg ${CAM_GROUP}L2MMU_CAM7 = 0xB80000081C08000000000002000000000000000200000001

 

As a test I moved the DDR memory to 1G between 0x40000000-0x80000000 and the processor access works fine.

Any ideas about why the above TLB entry does not work?

Outcomes