TLB mappings above 4G in tcl

[reedy]

I am trying to setup a baseboard project that runs out of SRAM that initializes the DDR controllers and then performs tests on the memory. I am using a T4240QDS to test. The following memory map is desired:

# 0x00000000 0x001FFFFF TLB1_1 SRAM 2M
# 0xFE000000 0xFEFFFFFF TLB1_2 CCSR 16M

# 0x200000000 0x3FFFFFFFF TLB_7 DDR 8G

The DDR initialization appears to be working correctly as I can read and write the memory via the code warrior memory view. When I add the following TLB entry so the processor can access the DDR memory the program gets a program exception.

# define 8GB TLB entry 7 : 0x200000000 - 0x3FFFFFFFF for SRAM1 cache-inhibited
reg ${CAM_GROUP}L2MMU_CAM7 = 0xB80000081C08000000000002000000000000000200000001

As a test I moved the DDR memory to 1G between 0x40000000-0x80000000 and the processor access works fine.

Any ideas about why the above TLB entry does not work?

[reedy]

Discovered some new information that may help.

Without the 8G TLB code warrior shows my tlb registers are:

"L2MMU_CAM1">0x7000000A1C08000000000000FE00000000000000FE000001
"L2MMU_CAM2">0x500000081C08000000000000000000000000000000000001

"L2MMU_CAM3">0x500000081C08000000000000001000000000000000100001
"L2MMU_CAM4">0x1000000A1C08000000000000FFDF000000000000FFDF0001
"L2MMU_CAM5">0x9000000A1C08000000000000E000000000000000E0000001

"L2MMU_CAM6">0x5000000A1C08000000000000FF80000000000000FF800001

"L2MMU_CAM7">0xB800000C1C08000000000002000000000000000000000000

With the only difference being the addition of 8GB TLB to T4240QDS_init_sram.tcl code warrior shows my registers are as follows:

"L2MMU_CAM1">0x7000000A1C08000000000000FE00000000000002FE000001
"L2MMU_CAM2">0x500000081C08000000000000000000000000000200000001
"L2MMU_CAM3">0x500000081C08000000000000001000000000000200100001
"L2MMU_CAM4">0x1000000A1C08000000000000FFDF000000000002FFDF0001
"L2MMU_CAM5">0x9000000A1C08000000000000E000000000000002E0000001
"L2MMU_CAM6">0x5000000A1C08000000000000FF80000000000002FF800001
"L2MMU_CAM7">0xB800000C1C08000000000002000000000000000200000001

As you can see for some reason the 2 is propagated to all the TLB's.

I decided to move the TLB7 initialization to software (main_SRAM.c -> main()) and everything works as expected. Since this works I will go down this path, however I am still interested in why the same cannot be accomplished in tcl initialization file.

Thanks,

Christian

[yipingwang]

Hello Christian,

Would you please also enable and capture CCS log and send it to me? I need to check the low level CCS action.

Please refer to the following procedure to enable CCS log.

Before connect to the target, please enable CCS log from "Run->Debug Configurations-><project>-core0_RAM_-Connect(Download)->Edit...->Advanced->Advanced CCS setting->Enable logging(Enable JTAG diagnostics)", and connect to the target from "Run->Debug Configurations-><project>-core0_RAM_-Connect(Download)->Debug”, the CCS log will be printed in the console panel in CodeWarrior IDE.

Note:

Please open the console panel from Window->Show View->Console, and if nothing displayed, please choose the correct session on the right top icon in the panel.

If the CCS log in the console is truncated, please enlarge the console buffer from Window->Preferences->Run/Debug->Console->uncheck "Limit console output".

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[reedy]

I don't see a place to attach a file but the following is what your probably interested in.

ccs_write_memory
coreh = [serverh:0;cc_index:0;chain_pos:1]
addr = [space:0x9a;size:4;address_hi:0x00000000;address_lo:0xfe0e00e4]
data: (size = 4)
00000001
ccs_write_memory; ccs_error = 0; duration=2 ms
cmdwin::reg regPPCTLB1/L2MMU_CAM1 = 0x7000000A1C08000000000000FE00000000000000FE000001
cmdwin::reg regPPCTLB1/L2MMU_CAM2 = 0x500000081C08000000000000000000000000000000000001
cmdwin::reg regPPCTLB1/L2MMU_CAM3 = 0x500000081C08000000000000001000000000000000100001
cmdwin::reg regPPCTLB1/L2MMU_CAM4 = 0x1000000A1C08000000000000FFDF000000000000FFDF0001
cmdwin::reg regPPCTLB1/L2MMU_CAM5 = 0x9000000A1C08000000000000E000000000000000E0000001
cmdwin::reg regPPCTLB1/L2MMU_CAM6 = 0x5000000A1C08000000000000FF80000000000000FF800001
cmdwin::reg regPPCTLB1/L2MMU_CAM7 = 0xB800000C1C08000000000002000000000000000200000001
cmdwin::mem i:0x00FE1241C0 = 0xf03f3f3f
ccs_write_memory
coreh = [serverh:0;cc_index:0;chain_pos:1]
addr = [space:0x9a;size:4;address_hi:0x00000000;address_lo:0xfe1241c0]
data: (size = 4)
F03F3F3F
ccs_write_memory; ccs_error = 0; duration=2 ms
cmdwin::mem i:0x00FE1241C4 = 0xff003f3f
ccs_write_memory
coreh = [serverh:0;cc_index:0;chain_pos:1]
addr = [space:0x9a;size:4;address_hi:0x00000000;address_lo:0xfe1241c4]
data: (size = 4)
FF003F3F
ccs_write_memory; ccs_error = 0; duration=1 ms
cmdwin::mem i:0x00FE124010 = 0x00000101

[yipingwang · Accepted solution]

Hello Christian Reedy,

In your CodeWarrior initialization file, please set MSR[CM] as 1 to configure the processor working in 64 bit mode.

# set CM=0 = 32-bit
    reg ${SPR_GROUP}MSR = 0x00000000

=>

# set CM=1 = 64-bit
    reg ${SPR_GROUP}MSR = 0x80000000

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[yipingwang]

Hello Christian Reedy,

Please check whether you configure LAW size for DDR correctly, in CodeWarrior initialization file for T4240QDS, LAW for DDR is configured as 2 G.

Would you please provided your modified CodeWarrior initialization file?

I will do further investigation for you.

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[reedy]

Attached modified initialization files.

[yipingwang]

Hello Christian Reedy,

In your CodeWarrior initialization file, you didn't define LAW configuration for DDR at all, please add this configuration in the "Local Access Windows Setup" section, please refer to the following.

  ## LAW0 to DDRC1
    # LAWBARH
    mem [CCSR_ADDR 0x000C00] = 0x00000000
    # LAWBARL
    mem [CCSR_ADDR 0x000C04] = 0x20000000
    # LAWAR
    # Memory complex 1
    mem [CCSR_ADDR 0x000C08] = 0x81000020
   

or

   # LAWBARH
    mem [CCSR_ADDR 0x000C00] = 0x00000000
   # LAWBARL
    mem [CCSR_ADDR 0x000C04] = 0x20000000
   # LAWAR
   Interleaved Memory Complex 1-3     

   mem [CCSR_ADDR 0x000C08] = 0x81700020

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[reedy]

In the file I originally sent (T4240QDS_init_sram.tcl) I attempted to setup the LAW registers on lines 117-123. I am attempting to map DDR to 0x2_00000000. Would'nt the code you sent map DDR to 0x0_20000000?

Thanks,

Christian

[yipingwang]

Hello Christian Reedy,

Please try whether this could be helpful

reg ${CAM_GROUP}L2MMU_CAM7 = 0xB800000C1C08000000000002000000000000000200000001

Enable Memory coherency required.

 0 Memory coherency is not required.

 1 Memory coherency is required. This allows loads and stores to this page to be coherent with loads and stores

from other processors (and devices) in the system, assuming all such devices are participating in the coherency protocol.

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[reedy]

memory coherency did not change the problem.