Working on the PLL configuration, I have read in the MPC5777MRM.pdf on page 1206 that:
"The system clock dividers are synchronized to each other such that the rising edges of the
lower frequency clocks are aligned with those of the higher frequency clocks. This,
however, imposes limitations on the division factors which can be used. In order for the
synchronization to work properly, each division factor must be selected such that its
value is an integer multiple of each division factor that has a lower value"
On page 1208, it is given a correct example of configuration on table 29-4.
However, I don't understand why CGM_SC_DC0[DIV] is choosen with value 3 since it is not a integer value of CGM_SC_DC3[DIV] which has a value of 2.
Moreover, is the order of the configuration of these registers important ?