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LS1021A-IOT: How to differentiate PORESET and HRESET from software?

Question asked by Jean-Francois Riendeau on Sep 14, 2016
Latest reply on Sep 14, 2016 by alexander.yakovlev

I'm working on a LS1021A-IOT reference board. I'd like to be able, from softwar,e to know whether the last boot was caused by a power-on (PORESET) or something else (HRESET), without using any additional hardware. I've scoured the Reference Manual but coud not find anything conclusive. The closest I could find was the Watchdog Reset Status Register (WDOG1_WRSR), that defines 2 bits:

  • TOUT (bit 1) : Timeout. Indicates whether the reset is the result of a WDOG timeout (0 = no, 1 = yes).
  • SFTW (bit 0): Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit (0 = no, 1 = yes)

However, this proves to be incorrect, because even after causing a software reset using the Watchdog Control Register (WDOG1_WCR), by clearing SRS (bit 4), neither of TOUT or SFTW were raised. Is there a register in the LS1021A (or some other board component) that I can query to obtain this information?

 

My final objective is to implement a persistent DRAM, as described in AN4531. In this application note, it was recommended to initialize the DDR controller on power-on, but bypass the initialization on subsequent resets.

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