I am creating tests for a customer's i.MX6Q board. We are having issues downloading data to DDR3 via JTAG. Our initialization script can properly initialize the DDR3 (RAM tests pass). We can download data to internal RAM. But, downloading via JTAG to DDR3 is unreliable. When it fails, it will fail at offsets of 0x4 and 0xc (only certain byte lanes will fail).
DATA 4 0x10000000 0x11223344 (read result = 0x11223344)
DATA 4 0x10000004 0x55667788 (read result = 0x55001688)
DATA 4 0x10000008 0x99AABBCC (read result = 0x99AABBCC)
DATA 4 0x1000000c 0xDDEEFF00 (read result = 0xDD001600)
CPU access to DDR is still okay and memory tests to DDR will pass. It is only JTAG access to DDR that seems to be affected.
Are there any i.MX6 configuration registers which would affect JTAG access to DDR?