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T1040 DD3L per lane write leveling

Question asked by Rainer Boschung on Sep 13, 2016
Latest reply on Nov 6, 2016 by Rainer Boschung


I am designig a board with T1040. For this desing do not use UDIMM, the SDRAM ar directly placed on the board. the SDRAM chip are placed an routed like a MicroDIMM. And I use SPD.

For me it is not clear how to setup the ddr board options  for my desing. I think I can do this the same way as it is done for the T1040RDB (u-boot ddr.c) but I is not clear how to adapt the per lane write leveling start values (DDR_DDR_WRLVL_CNTL_2/3[WRLVL_START_n]).


How can I determine those values for my design?

As far as I understood this has to be calculated:

WRLVL_START_n = CLK_ADJUST + CLK_propagation_pcb - DQSn_propagation_pcb

Is this correct or how should I calculate this?


Thanks for your support.