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Question, CheckList of i.MX7SD HW design

Question asked by AVNET JAPAN FAE (team share account) on Sep 12, 2016
Latest reply on Sep 16, 2016 by AVNET JAPAN FAE (team share account)

Dear team,

 

I would like to ask about the check list which is described in your HW design guide(IMX7DSHDG, Rev.0) of i.MX7SD.

Could you give your answers to the following questions?

(1)

In Table-7, we can find the writing about PVCC_GPIO_1P8_CAP pin. But we cannot find where the PVCC_GPIO_1P8_CAP in other technical documentation of i.MX7.

What is the PVCC_GPIO_1P8_CAP?

(2)

In Table-8, the following description is stated.

“4. If VDD_SNVS_IN is directly supplied by a coin cell, a schottky diode is required between VDD_HIGH_IN and VDD_SNVS_IN. The cathode is connected to VDD_SNVS_IN.

Alternately, VDD_HIGH_IN and VDD_SNVS_IN can be tied together if the real-time clock function”

But we cannot find VDD_HIGH_IN pad on i.MX7SD. What the VDD_HIGH_IN mean?

Could you show me which part in SABRE is the related to this description?

(3)

In Table-8, the following description is stated.

“5. If boundary scan test (BSDL) will be used, the following supplies must be powered: PCIE_VP, PCIE_VPH, PCIE_VPTX”

Could you show me how the pads should be handled actually?

Should those pads be connected to the power voltage which datasheet describes?

(4)

As for Table-12,

How should USB related signals be treated in the case of not using USB?

(5)

In Table-14, the following description is stated.

“1. The TEST_MODE input is internally connected to an on-chip pulldown device. The user must tie this signal to GND.”

We can find that the TEST_MODE pin is connected to GND through 100K ohm register.

Which is the correct?

 

Thanks,

Miyamoto

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