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About address space size of chip select in i.MX6.

Question asked by Keita Nagashima on Sep 12, 2016
Latest reply on Sep 15, 2016 by Keita Nagashima

Hi All,

 

There is below description about ADDRS3[10] bit in IMX6DQRM(Rev.2)

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Active Chip Select and Address Space.
Each of the ACT_CSx represents one of the four chip selects of the EIM.

When ACT_CSx=1'b1, the corresponding chip select is active and has a valid address space according to its address space configuration determined by ADDRSx[10] bits ADDRSx[10] is setting the space for each chip select which is active.

The address space of the first active chip select must be the largest one, the following active chip select address spaces may be equal or smaller.
Total address space size is 128 MByte.
The supported configurations are:
CS0(128M), CS1 (0M), CS2 (0M), CS3(0M) [default configuration]
CS0(64M), CS1(64M), CS2(0M), CS3(0M)
CS0(64M), CS1(32M), CS2(32M), CS3(0M)
CS0(32M), CS1(32M), CS2(32M), CS3(32M)
Address Space Configuration options (ADDRSx[10]):
 00 32 MByte
 01 64 MByte
 10 128 MByte
 11 Reserved

 

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But, my customer has already connected the like below on their custom board.

<Current customer's system> 

- CS0, 32M, 0x08000000
- CS1, 64M, 0x0A000000
- CS2, 32M, 0x0E000000

 

[Q1]

Is it OK the above system?

(Now, it looks right operation as allocation and access on their custom board)

 

Or, is it necessary to change as follows?

CS0(64M), CS1(32M), CS2(32M)

 

[Q2]

Is there any limitation or problem in their system formation?

 

Best Regards,

Keita

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