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About EIM read access timing in i.MX6DQ.

Question asked by Keita Nagashima on Sep 12, 2016
Latest reply on Sep 13, 2016 by Yuri Muhin

Hi All,



The i.MX6 reads the data from external FPGA via EIM bus.



When the FPGA outputs the WAIT & DATA signals to i.MX6, must the FPGA output the signals with the falling edge of EIM_BCLK from i.MX6?

(Because i.MX6 latches the WAIT & DATA signals with rising edge of EIM_BCLK.)



Best Regards,