MCF51 SPI Slave, Interrupt on rising edge of SS signal

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MCF51 SPI Slave, Interrupt on rising edge of SS signal

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mherold
Contributor I

I'm using the MCF51QM as a SPI slave with DMA data transfer. Is there a way to generate an interrupt at the end of the transmission, when the SS signal goes high? Unfortunately in this application it's not possible, to connect the SS signal to an additional GPIO input.

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TomE
Specialist II

"Figure 40-36. Basic Flow of SPI Transmission by DMA" gives the expected operation.

It is assumed that you know prior to setting up a transfer, exactly how long it is going to be.

Either the protocol has fixed sizes, or some previous message provided the length of subsequent transfers.

You then program the DMA controller to exactly that length, and wait for the DMA interrupt to say it has finished.

If the "protocol" in use doesn't work this way, then this hardware doesn't really support it.

Handling that sort of protocol is better suited to receiving the data with interrupts (with or without the FIFO). If you can't do that then it is usually either due to the SPI speed being too high relative to the CPU) or the CPU being locked out in other interrupt service routines. This CPU has 7 interrupt levels, so you could run the SPI at a higher level than everything else.

Otherwise you may have to poll for the end of the message. Does this chip allow the GPIO functions of a pin to still work when the pin is doing something else, so can you POLL the SS pin via a GPIO?

"44.4.1.2 Operation when another on-chip module controls pin" implies you can read the pin state when it is in use for something else. So I think you can poll the pin from software. All pins can also generate interrupts. There's nothing to say that pin interrupts work when "another on-chip module controls pin", but there's nothing to say it doesn't work either. You may just have to write some code and see if it does.

Tom

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yibbidy
Contributor V

I've not used this part myself but a quick look in the reference manual shows that the only receive interrupts are for when the buffer is full (when not using the FIFO), or when the FIFO is full.  Of course you won't get these interupts if using DMA.

If you can modifiy the masters SPI transmission, perhaps you could make use of the Match Register Interupt, by getting the master to transmit a unique word at the end of transmission.

Other than that it looks like connecting !SS to a GPIO is the only way.

Cheers, Shaun

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