Hi all, I am using custom based board based on LS2085A QDS. We are using Serdes 1 protocol = 0x37. The protocol sums up below:-
Serdes lanes:-
Serdes protocol
XFI1 | XFI2 | QSGMIIc | QSGMIId | PCIe2 |
From the above interfaces we are not using E lane (QSGMIId) . The QSGMIIc (F lane) signals are connected to Quad PHY IC (F104S8A) and four physical ports are brought out of the board.
For getting the QSGMIIc interface working we did the following changes:-
1) Selected 0x37 as serdes 1 protocol.
2) Flashed and Booted Management Complex firmware
3) Booted kernel, We are using EAR6 SDK
4) QSGMIIc uses MAC9 to MAC12 , therefore we created four PHY nodes in dts file and added this phy handle to corresponding MACs.
But still our QSGMII interface doesn't seems to work. We are using LS2085aQDS kernel dts and dtsi file as our reference. Is there anything else we are missing from the above steps.
Can anyone validate our procedure or provide any steps for configuring QSGMII interface ?
