My current setup uses the SCI2 Tx and Rx signals for data transmission and a separate I/O signal which indicates a request to send data.
When my request to send data signal goes high (logic 1) then my source code puts a flag byte in the SCI2 Data register to be transmitted. This should occur every time the request to send data is received.
Unfortunately, this only works for the first request to send data. When the second request occurs, I can see my code put the flag byte into the SCI2 data register and set the transmission to begin, and I can also see that the transmit complete bit in the status register gets set to a 1, indicating that it has finished sending the byte on the Tx line.
However, when I probe the Tx signal with an oscilloscope, nothing is actually being put out on the bus.
As I have mentioned this works once just fine, but the second time nothing will get out on the bus at all. Which results in my request to send data signal never being acknowledged and my whole system locking up.
Is there any reason why the hardware would think that the data had been transmitted, when it in fact had not been?