HC08GP32 - LVI bit not set in SRS on apparent LV event

[peg]

Hello,
I have a machine with 13 modules in it each containing an HC908GP32.
One of these is intermittently resetting.
The LVI is enabled and set for 5V operation. (32k768 xtal 7.3MHz buss)
As these are all on a 485 buss I made a serial command to report the SRS register.
After POR the SRS reports $80 as expected.
After an external reset on the reset pin it reports $40 as expected.
After the mysterious event it reports $00 (already cleared by a prior read).
I know it has reset as events that only happen in the initialisation code occur.
I found that causing a very short power outage (of 24V supply that feeds a 5V regulator) I could also
create this erroneous SRS code.
Now on the bench I can simulate this and also monitor the reset pin.
A 35ms duration rail dip to about 2 volts causes the reset pin to be asserted as it passes through 4 volts or
so as expected. It remains asserted for the expected 4096 + 32 cycles (approx 130ms) after rail recovers.
This is all expected for a LVI reset.
What is not expected is for the LVI bit to not be set in SRS!
If I allow the dip to occur for longer and the rail to droop further I will have $80 in the SRS (POR)

What have you got to do to get the LVI bit set?

I also got an $80 once I think so from the above it seems like I might have a poor connection somewhere.

I would be much happier though if someone could explain why I am not getting the LVI bit set.

I have seen the LVI bit set in another product of ours that monitored the SRS after every reset and indicated every non standard event. This was with a QY2.

[peg]

Hi again,

I should point out that 12 of the 13 modules have the same programme and the problematic 13th one has a quite different programme. Odds say it has something to do with the code. This is why I would really like to know what the reset source is.
To make things worse all 13 are on a turret 2m above the floor that spins around and I have limited access to the machine (time). It won't fail on the bench, except for disturbing the power supply. Grrrrrr!

[peg]

Hello - still struggling.

I have done some more thorough and scientific testing today.
I lower the power supply from 5volts to 3.6 for about 20ms.
This generates the expected reset but DOES NOT set the LVI bit in the SRS register!

I have done this on 3 different boards that use GP32. Under NO circumstances have I been able to get the LVI bit set EVER!

To further test this I set LVIRSTD in CONFIG1.
This should still allow the LVI to work but not generate a reset.
Now I can check if I have a LVI condition via LVIOUT in LVISR.
But at 3.5V the reset is still generated so I can't check it????
Also on recovery from this, everytime I get $10 in SRS??? ILOP???

I have taken this up with Freescale Technical support but have not reached a solution yet.

If anybody has any experience with this please let me know, even if it is "I used it and it seemed to work fine to me".

[peg]

Hi - still babbling away to myself here it seems.

Ake from Freescale prooved that it all works fine on a demoboard that uses a canned oscillator for the clock.
So I connected an oscillator and wrote a similar test programme to his.
Everything works fine as per the book.
Lower the voltage, at about 4.2volts it goes into reset.
Raise the voltage and when it gets to 4.3ish it comes out of reset and the LVI bit is st in SRSR.
Also disabling the reset allows you just to read the LVI status from the LVISR register just like it says in the datasheet.
Now if I add some PLL setup code and go back to using the 32kHz crystal I start to get some strange results but not as before. Now the LVI bit works but the POR bit only gets set sometimes.
Still needs further work to make the test code more like the original code and hopefully bring on the original symptoms.
However the problem seems to be the slow startup of the crystal oscillator and how quickly you read the SRSR after the code gets going and the PLL gets fired up.

Still hoping somebody can help me out here.....
Ake is hopefully going to test again with the 32kHz oscillator on his demoboard fired up.

[bigmac]

Hello Peg,

It did occur to me that your original problem is like there is an external reset device that operates prior to the internal low voltage detect - but I guess this is not the case.  Unfortunately, I do not have a board on which to do tests.

Regards,

Mac

[peg]

Hi Mac,

There is nothing connected to reset.
If there was and it was causing an issues I would see this recorded in the SRSR.

I have discovered my issue with the LVI bit in the SRSR.
When I added the serial command to read the high registers (including SRSR) I used parts of an existing (10 year old) debugging command that allowed me to view any RAM location. Unfortunately, this command read the address, generated the high nibble in ASCII then READ THE ADDRESS AGAIN to generate the low nibble ASCII. This of course meant the high nibble worked but the low nibble would always read as zero. Oh Dear! Guess where the LVI bit is located. (The POR and PIN are in the high nibble)

There still seems to be some minor issues with this register whan using a 32k crystal but all in all it works as advertised.

Now back to the machine to see if I can trap the cause of the mysterious reset now that my command works properly.


Message Edited by peg on 2008-07-04 07:06 PM