David Payne

HC08GP32 - LVI bit not set in SRS on apparent LV event

Discussion created by David Payne on Jun 20, 2008
Latest reply on Jul 4, 2008 by David Payne
Hello,
I have a machine with 13 modules in it each containing an HC908GP32.
One of these is intermittently resetting.
The LVI is enabled and set for 5V operation. (32k768 xtal 7.3MHz buss)
As these are all on a 485 buss I made a serial command to report the SRS register.
After POR the SRS reports $80 as expected.
After an external reset on the reset pin it reports $40 as expected.
After the mysterious event it reports $00 (already cleared by a prior read).
I know it has reset as events that only happen in the initialisation code occur.
I found that causing a very short power outage (of 24V supply that feeds a 5V regulator) I could also
create this erroneous SRS code.
Now on the bench I can simulate this and also monitor the reset pin.
A 35ms duration rail dip to about 2 volts causes the reset pin to be asserted as it passes through 4 volts or
so as expected. It remains asserted for the expected 4096 + 32 cycles (approx 130ms) after rail recovers.
This is all expected for a LVI reset.
What is not expected is for the LVI bit to not be set in SRS!
If I allow the dip to occur for longer and the rail to droop further I will have $80 in the SRS (POR)

What have you got to do to get the LVI bit set?

I also got an $80 once I think so from the above it seems like I might have a poor connection somewhere.

I would be much happier though if someone could explain why I am not getting the LVI bit set.

I have seen the LVI bit set in another product of ours that monitored the SRS after every reset and indicated every non standard event. This was with a QY2.

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