i am new to the Kinetis K60_120 MHz family. we are looking at this part to implement a memory controller interface to NAND flash with ECC.
From reading the K60 Sub-Family reference manual with addendum, i think i understand how the ECC is being used to correct the data and how the main data is organized in conjunction with the ECC.
however, i do not see any mention about the possibility of ECC bit itself got flipped and how to protect and correct the flipped ECC bit in the spared area? The flipped possibility is small as the spared area is a lot smaller than the main data area, but it can happen.
Atmel SAM3x Nand flash controller has the parity associated with the ECC in the spare area where application can do the correction.
I wonder if Kinetis K60 has something like that.