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[P2020] What is th core0/1 state when TRIG_OUT signal raises (using event trigger) ?

Question asked by Remy Ritchen on Sep 7, 2016
Latest reply on Sep 12, 2016 by Remy Ritchen

TRIG_OUT is asserted when TOSR[SEL] is non-zero and associated debugging event is triggered. READY_P0 indicate core state (ready / debug / etc) TRIG_OUT and READY_P0 are multiplexed.

When debugging event raises, what are the core state ?

- Core0 keeps in ready state ? becomes debug ?

- Concerning core1 ?

I search a mean to freeze external clocking source (RTC) for Core Time Base and Decrementer (see figure 4.7 - reference manual) when Core0 enters to debug state (thanks to debug tools). READY_P0 seems to be adapted signal but in case where event trigger is also used, what is the behavior ?