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EIM read hold time with continuous BCLK

Question asked by Andrew Dyer on Sep 6, 2016
Latest reply on Sep 6, 2016 by igorpadykov

On i.MX6 DualLight we are using synchronous EIM accesses with continuous BCLK @104MHz to talk to an FPGA.  We have a setup on the board that seems to work over temperature in testing.  Looking at the FPGA timing reports, if the FPGA is in best case process corner it does not meet the 2ns hold time (WE19, figure 15, section of datasheet Document Number: IMX6SDLCEC).


Are the setup/hold timing numbers correct for continuous BCLK where there is a DLL in the i.MX6 to lock to the read clock?