I'm at a loss as to why a section of code raises an ISI exception even though the TLB has been mapped with an UX permission. I would appreciate any ideas/suggestions as to what I could be missing. Thanks!
Have you checked twice SRR0, SRR1 and MSR register contents, when the exception is taken?
I checked them. The SRR0 points to a thread running in a memory section that was mapped with Memory coherence required, UX and UR bits are set to 1. SRR1 is shown to be 0x0000F902 (PR bit is set).
That’s why I didn’t understand why an ISI exception happened.
The ISI exception goes away when I set the SR bit (supervisor read) to 1. Why would that be?
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