During debug, I found that I should add a 4us delay between two times of write data to SPI. If delete this delay,
will cause some of data to be lost.
My code please refer to attached.
sysSpiDrvInitFPGA: is used to initiate SPI controller;
sysSpiWriteDataFPGA: is used to send data to SPI;
In my mind, I only need to check SPIE_DON bit of SPIE register between two times of transmit, not need to
add a delay. But from test, I should add a delay, only check SPIE_DON bit of SPIE register is not enough.
Could you please help to give some suggestions?
Original Attachment has been moved to: sysFslSpi.c.zip