Not able to Re-initialize Watchdog clock as OSCCLK in S12G micro

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Not able to Re-initialize Watchdog clock as OSCCLK in S12G micro

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ganeshvijayakum
Contributor I

Hi,

 

I have a problem in re-initializing the COPOSCSEL0  register.

I do work on S12G micro controller and I have bootloader and application flashed on the micro.

 

Here, In bootloader I do initialize the CPU registers as shown below,

   CPMUCOP   = 0x44;

   CPMUPROT    = 0x26;
   CPMUCLKS    = 0x80;
   CPMUOSC     = 0x80;
   CPMUREFDIV  = 0x80;
   CPMUSYNR    = 0x01;
   CPMUPOSTDIV = 0x00;
   CPMUPLL     = 0x00;

while (!UPOSC){}

CPMUCLKS   |= 3;

 

Now, in application I  do initialize the CPU registers in the same way except watchdog.

   CPMUPROT    = 0x26;
   CPMUCLKS    = 0x80;
   CPMUOSC     = 0x80;
   CPMUREFDIV  = 0x80;
   CPMUSYNR    = 0x01;
   CPMUPOSTDIV = 0x00;
   CPMUPLL     = 0x00;

while (!UPOSC){}

CPMUCLKS   |= 3;

   CPMUPROT    = 0x01;

 

I am initializing the CPMUCOP = 0x44 far later the initialization of CPU clock regusters.

 

So now, please look into the observations below,

1) When I flash application only, and monitor the CPMUCLKS register value at run time, I can observe 0x83,

2) When I flash bootloader only, and monitor the CPMUCLKS register value at run time, I can observe 0x83.

3) But when both the bootloader and application are flashed on to the board, and when the control is in application now I can read CPMUCLKS value as 0x82 only.

 

So in the 3rd observation I can see COPOSCSEL0 is not set, but I need that bit to be set because OSCCLK should be used for COP on my project.

 

So, One more observation I have made in application is I am initializing the CPMUCOP far later the initialization of CPU clock regusters.

 

What I observed is when control jumps from bootloader to application watchdog is already initialized and when I try to set the COPOSCSEL0 bit CPMUCOP register, It is not  at all set.

What should I do to set the COPOSCSEL0 bit in application when bootloader is present.

 

Is there any dependency between the COPOSCSEL0  and CPMUCOP registers?

 

Thanks in advance,

Regards

Ganesh Vijaya Kumar P.

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iggi
NXP Employee
NXP Employee

Hi Ganesh,

There is an important note in the S12G datasheet below CPMUCLKS register description:

"After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful."

So something like this we have in our SW examples for setting PLL:

CPMUCLKS = 0B10000011;

if(CPMUCLKS != 0B10000011) {asm nop;}

Next, in your third observation, when you combine bootloader and application, do you write CPMUCLKS twice?

It would be better to have it once write and then read back.

The dependency is that "a change of the COPOSCSEL0 or COPSOCSEL1 bit (writing a different value)..., re-starts the COP time-out period.

Regards,

iggi

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