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LPC4330 BASE_M4_CLK

Question asked by Tom Saluzzo on Sep 2, 2016
Latest reply on Sep 23, 2016 by jurgen geerlings

Listed below are the steps that I think we have to take in order to change the BASE_M4_CLK frequency to 168 MHz. Please review and let me know if this will work.

We want to run the SDRAM clock at 84 MHz and the CPU clock at 168 MHz. Therefore, we have to change the BASE_M4_CLK to 168 MHz. The procedure for changing the clock is on page 166 of the User Manual.

1)    Select the IRC as the BASE_M4_CLK source:
Write 0x01000000 to the BASE_M4_CLK Control Register at Address 0x4005006C.
2)    Enable the crystal oscillator:
Write 0x00000000 to the Crystal Oscillator Control Register at Address 0x40050018.
3)    Wait 250 uS.
4)    Reconfigure PLL1. Select the M and N divider values to produce the final desired PLL1 output frequency foutpll. Select the crystal oscillator as the clock source for PLL1.
We want the final PLL1 output frequency to equal 168 MHz. Our crystal frequency is 12 MHz. Select M = 14 and N = 1.
Write 0x060E0040 to the PLL1 Control Register at address 0x40050044.
5)    Wait for PLL1 to lock.

6)    Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL = 0).
This was done is step # 4.
7)    Select PLL1 as the BASE_M4_CLK source.
Write 0x09000000 to the BASE_M4_CLK Control Register at Address 0x4005006C.
8)    Wait 50 uS.
9)    Set the PLL1 P-divider to direct output mode (DIRECT = 1).
Write 0x060E00C0 to the PLL1 Control Register at address 0x40050044.

 

 

Refer to Section 13.2.1.1 on page 166 of the LPC4330 User Manual. Step 6 says to “Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL = 0)”. I program DIRECT = 0 and PSEL = 0 in Step 4 of the procedure so I don’t understand what Step 6 is for. What should the values for DIRECT and PSEL be in Step 4?

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