The answer depends on SPI controller type, used in the processor, which in turn depends on the processor in question.
For example, for devices from "Networking" product segment (MPC8xxx and QorIQ) - there are a number of processors, where SPI controller has 4 pins. The last, 4th pin is used as "Slave Select" input, if you assert this input when the SPI controller is master, than special exception to core will be generated, meaning that another SPI master is currently transmitting on the SPI bus, so the core may detect this situation. This allows implementing multi-master SPI bus.
Have a great day,
Alexander
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