I am facing problems when transmitting data via SPI when the controller acts as SPI slave. I configured the SPI module to use RX and TX FIFO buffers and disabled all interrupt requests.
When transmitting data in polling mode the SPIx_SR[TFFF] bit will never be cleared, although I am writing more than 4 values to it. My idea is to write to the TX buffer as long as it is not full, and wait in a busy loop for free space.
Is this a known issue or am I just doing something wrong?