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DDR3 multiple bit error in P1012

Question asked by Carlos Terleira Irazábal on Sep 1, 2016
Latest reply on Sep 20, 2016 by Carlos Terleira Irazábal

Hello,

I am using a P1012 and a DDR3 memory.

I am using write leveling.

 

The following documents are referenced in this question:

AN4039 Rev. 4, 11/2014

P1012RM Rev. 6, 01/2013

 

The uP shows multiple bit error in DDR3 ECC with the initial configuration (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] = 1/4 and DDR_WRLVL_CNTL[WRLVL_START] = 1/8).

We have changed the initial configuration. Now the value of DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is the same as DDR_WRLVL_CNTL[WRLVL_START] = 1/8,  it appears to work properly. It doesn't work with 0 or 1/4 values.

 

1) When a DDR3 multiple bit error is detected the uP stop working, even when interruptions are disabled. Is there any way to recover from this error?. I have seen that the only way is to disable error detection and correction.

 

2) Is DDR_WRLVL_CNTL[WRLVL_START] totally equivalent to DDR_TIMING_CFG_2[WR_DATA_DELAY]?

I´m asking this question to know if the following sentences also applies to DDR_WRLVL_CNTL[WRLVL_START]:

  2.1) AN4039/Table 8/WR_DATA_DELAY field - "The value selected for the write data delay should closely follow the DDR_SDRAM_CLOCK_CTRL [CLK_ADJUST] field value."

Also AN4039/Table 14/CLK_ADJUST field - "So, if WR_DATA_DELAY is not changed to match the CLK_ADJUST change, an offset is added between MCK and DQS."

So I suppose that the value for DDR_WRLVL_CNTL[WRLVL_START] shall be the same to DDR_SDRAM_CLK_CNTL[CLK_ADJUST].

  2.2) P1021RM/Section 8.4.7 DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2)/WR_DATA_DELAY field - "However, for WR_DATA_DELAY settings of 0 clocks and 1/4 clocks, the write preamble is driven low for the entire DRAM cycle. If the preamble needs to switch high first (to meet DDR3 specifications), then these values should not be used."

So I suppose that the values "0" and "1/4" shall not be used for DDR_WRLVL_CNTL[WRLVL_START] using DDR3 memories.

 

 

Thanks and regards

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