I'm using Kinetis Design Studio 3.0.0 for the controller MK02FN128VFM10. I'm using 16 bit differential configuration for ADC for my project.
As mentioned in the datasheet, with no hardware averaging, maximum ADC conversion rate of 461 KSamples per second can be attained. But in my case, with this specification I'm getting 90 KSamples per second.
So how to achieve the maximum ADC conversion rate?
Also, in the datasheet, 'To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.' is mentioned. These settings are already done, so according to it maximum ADC conversion clock frequency is in operation.
How to tackle with this issue? Please help.